Tell me about clocking RAMs and Flip Flops in the same CLBs?
Answer:
In the XC4000-derived architectures, the LUT RAM and the FFs-or-latches have independent clock inversions, so within a single CLB you can write into the RAMs on the clock rising edge and capture or latch the RAM outputs on the falling edge. No such luck in Virtex-derived architectures including Spartan-II. There, there is only a common clock inversion for both LUT RAM and FFs, and if you write into the RAMs on a rising edge, you can only clock the FFs on the rising edge, and (as far as latches) they close on the rising edge too. So you can't clock the FFs/latches on the other edge as with xr16 on XC4000. If you want to, you have to put the FFs/latches in another column of CLBs, and the extra interconnect delays hurt.
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