Tell me around clocking RAMs and Flip Flops surrounded by impossible to tell apart CLBs?
Answer:
In the XC4000-derived architectures, the LUT RAM and the FFs-or-latches hold independent clock inversions, so within a single CLB you can write into the RAMs on the clock rising lip and capture or latch the RAM outputs on the falling border. No such luck in Virtex-derived architectures including Spartan-II. There, in attendance is only a adjectives clock inversion for both LUT RAM and FFs, and if you write into the RAMs on a rising edge, you can simply clock the FFs on the rising edge, and (as far as latches) they close on the rising fringe too. So you can't clock the FFs/latches on the other edge as next to xr16 on XC4000. If you want to, you have to put the FFs/latches within another column of CLBs, and the extra interconnect delays hurt.
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